This invention relates to read-only-memories and more particular to a read-only-memory addressable by binary coded decimal (BCD) data.
Read-only-memories are now well known in the art and, during the past few years, read-only-memories (ROMs) have seen extensive use in calculator and microprocessor chips implemented in metal oxide silicon (MOS) technology. In these prior art applications, the read-only-memories have been provided by an array of memory cells which are typically responsive to an address contained in an address register or program counter for outputting an instruction word or program code in response thereto. The address in the address register or program counter has typically been in binary format, which of course, may be expressed as an octal, hexadecimal or binary number.
Disclosed herein is a calculator system which incorporates the BCD decoder ROM of my invention. As will be explained in more detail, provided is a main ROM or first ROM which is responsive to a binary address in a program counter for outputting instruction words and a second ROM is responsive to a binary coded decimal address in another address register for outputting program codes. The second ROM may be addressed by the operator keying-in appropriate commands at the calculator's keyboard. As will be seen, this addressing may be done by the use of appropriate labels or by entering a relative address into the calculator system from the calculator's keyboard. Inasmuch as this calculator, and for the matter most calculators, is provided with a decimal keyboard, the addresses used to address the second ROM are preferably BCD addresses. If, however, second ROM were provided by a conventional ROM of the type heretofore known in the prior art, then approximately six sixteenths of the total ROM area would not be utilized by the BCD addressing, and therefore would be wasted. Alternatively, the BCD address could be converted to hexadecimal and a conventional ROM used, but then circuitry to performm the BCD-hex conversion would tend to increase the size of the chip.
It is therefore one object of this invention to provide a ROM responsive to a BCD address. It is another object of this invention to reduce the amount of wasted space which would exist in a conventional ROM addresses only by BCD addresses. It is yet another object to eliminate the need for BCD to hexadecimal conversion circuitry.
The foregoing objects of this invention are achieved as is now described. A matrix or array of memory cells having column and row lines is addressed by decoders for the row and column lines thereof. The row and column decoders typically have a cascaded arrangement of differing levels. All the decoders on any given level decode the same bits of the BCD address in an address register. The bits decoded by a decoder at any given level preferably correspond to a number in base ten which is a prime number. That is, these decoders may be one-out-of-two, one-out-of three, one-out-of five, one-out-of-seven, one-out-of-eleven or the like decoders. These prime numbers for each level are a factor of the total number of program codes stored in the BCD ROM. In the embodiment disclosed, 5,000 program codes are storable in the BCD read-only-memory, with the row decoder comprising three levels of cascaded one-out-of-five decoders for providing a one-out-of-125 row decoder. The column decoder comprises three levels of cascaded one-out-of-two decoders and a cascaded one-out-of-five decoder for providing a one-out-of-40 column decode. It should be evident, moreover, that the particular number of program codes in a given BCD ROM and the relative sizes of the column and row line decoders are design choices within the scope of this invention.